1. Field of the Invention
The invention relates to a memory cell of a semiconductor device, and more particularly to a dynamic random access memory (DRAM) cell layout for arranging deep trenches and active areas and a fabrication method thereof.
2. Description of the Related Art
A dynamic random access memory (DRAM) cell typically includes a memory cell coupled to a storage capacitor. Generally the storage capacitor is formed within a deep trench etched into a semiconductor substrate. The storage capacitor is accessed using an access transistor which allows charge to be stored in the storage capacitor or retrieves charge from the storage capacitor depending on whether the desired action is a read or write function. For a buried strap type trench capacitor, dopant outdiffusion near a wordline can cause a short channel effect in the access transistor channel, thus reducing subthreshold conduction and causing a fail in retention time.
FIG. 1 is a conventional DRAM cell layout. Deep trench capacitors 10 are disposed under passing wordlines 12. Access transistors 14 are electrically coupled to storage nodes 16 of the trench capacitors 10 through diffusion regions 18 which may be either a source or a drain of the access transistors 14. Diffusion regions 20 are electrically connected to bitline contacts 22 which connect to bitlines (not shown) to read and write to the storage nodes 16 through the access transistors 14. Access transistors 14 are activated by the wordlines 12. When voltage is applied to the wordlines 12, a channel below the wordline 12 conducts and allows current to flow between diffusion regions 18 and 20 and into or out of the storage node 16. Wordlines 12 are preferably spaced across the smallest possible distance to conserve the layout area. The smallest possible distance is typically a minimum feature size “F”.
FIG. 2 is a cross-section along line 2—2 of FIG. 1. Elements of FIG. 2 are labeled as described in FIG. 1. The storage nodes 16 are isolated from a doped well 24 by a dielectric collar 26. A shallow trench isolation (STI) 28 is provided over the storage nodes 16 to electrically isolate the passing wordlines 12 formed above storage nodes 16. The diffusion region 18 of the access transistor 14 is connected to the storage node 16 through a buried strap (BS) 32 and a BS out-diffusion region 30. Considering an overlay tolerance effect, a BS merge phenomenon easily occurs to cause a short channel effect in a channel region 34 underlying a gate electrode 36 of the access transistor 14.